Within digital ASIC/SoC engineering, MindTree has the in-depth expertise with verification and testing to deliver solutions tailored to your requirements.

Spec-to-RTL

MindTree works as your engineering partner, starting with specifications, and going on to provide functional implementation and verified RTL.



RTL Design Flow

Spec-to-RTL

Verification
MindTree provides the right solution for complete outsourcing of design verification, or simply supplementing in-house verification efforts.

We have assisted with multiple tape out designs, and possess in-depth expertise with several advanced verification methodologies, including:
  • HVL (VERA, Specman)-based verification
  • C++ and Testbuilder-based verification
  • C-based verification (processor program and model)
  • Assembly Language-based verification (for processor sub-systems
  • RTL-based verification

Verification

DFT
Reduction of test times while comprehensively covering silicon structures can reduce overall testing costs. MindTree helps you with a range of DFT services such as scan insertion and stitching, meeting coverage goals, compression of test vectors, die and package testing, fault grading, and more.

NetList/RTL to GDS-II
MindTree knows what it takes to tape out designs to TSMC, UMC, SMIC, SCM, and more. We take on the responsibility of delivering GDS-II to the foundry of your choice, allowing you to focus on core competencies like designing features and functionality.

GDSII Design Flow


GDSII Design Flow
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